Robert James Stewart

I was a student at Heriot-Watt University from 2004 to 2013. In my MEng research I compared Big Data MapReduce query languages (APPT 2011).  In my PhD research I developed and verified a functional DSL for fault tolerant massively parallel computing (JFP 2016).

I became a Research Associate on two EPSRC projects: SerenA exploring how to facilitate chance encounters between researchers through semantic web and automated reasoning technology, and Rathlin researching programmable embedded platforms for remote and compute intensive image processing applications. I then became a Research Fellow then latterly the Co-Investigator on the EPSRC Border Patrol project to make the design of hardware systems resiliant against hidden malicious functionality.

I then became an Assistant Professor in 2018, before being promoted to an Associate Professor in 2022. I am a member of the Dependable Systems Group. I supervise PhD students on topics including processor architectures, memory management, functional programming and AI accelerators.